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Time Digital Converter(TDC) are usually be used to measure time interval of a seqeuence of events. The most well-known application of TDC may be the Time of Flight (ToF) measurement. Many Lidars are constructed based on the direct ToF principle: a laser pulse is transmitted and the reflected pulse is received. The time interval between transmitting and receiving a pulse is measured and the distance can be calculated.
In this project, a 4-channel TDC will be implemented on the Cmod A7 35T. It has 4 inputs, which can receive pulse signal of LVCMOS33 format. The on board 12MHz clock is used as the time base of the TDC. A Microblaze is also included in the design. The measurement will be read and parsed by the Microblaze and printed through the uart at 115200 baudrate. A serial termianl is required on a host PC to display the result.
Artix-7 35T is a relatively small device and has limited resource of on-chip block memory. However, we may need many RAMs to store code and measurement. Moreover, a C standard library function like prinf() is also required to print the measured timestamp, which needs a large stack size. Fortunately, Cmod A7 35T has a 512KB SRAM on board. Therefore, the SRAM is used to store the code, data and stack/heap. The spared block memory can be used as high speed buffer of the TDC module.Measurement Principle
Each pulse arriving on the inputs will be assigned to a timestamp. The origin (zero) of the timestamp is the time when the TDC module is initialized. Time interval can be calculated by substracting two timestamps.Block Design
1. Download and install board definition file of the Cmod A7 35T
2. Create new RTL project, and select Cmod A7 35T in the board tab
3. Create Block Design and add Microblaze
After adding microblaze, click run block automation, accept the default settings.
4. Drag & drop System Clock, Cell RAM and USB-Uart from the board tab into the block design.
5. Change cache settings of the Microblaze
Select "Address Editor" in the Vivado, change the range of axi_emc_0 to 512K, and take note of the base/high addresses of the axi_emc_0.
Then double click the Microblaze, enable "use instruction and data caches" and
change the settings on pages as follows:
6. Add TDC IP and AXI Stream FIFO
The TDC module is packed as an IP and can be easily integrated into a block design. Add the 4 channel TDC IP and the AXI Stream FIFO. The TDC IP requires a 100MHz clock as time base. When we added system clock in the previous steps, a clock wizard with 100MHz output is automatically added into the design. Connet the 100MHz clock to the clk_in1 of the TDC IP. The AXIS FIFO is used here to receive raw measurement data output by TDC IP. Double click the FIFO, and deselect the "Enable transmit data" and set the receive fifo depth to 8192. After all, connect the TDC's MAXIS_RAW32b port to the AXIS FIFO
7. Run Connect Automation
8. Make the 4 hit inputs of the TDC external
Add 4 input ports and connect them to the TDC's 4 inputs and write contraints for these inputs
Note: additiona timing constrains are also needed to achieve timing closure.Resouce Utilization
After Impelementation, the device view is as follows:
Programming under Vitis
We need write a simple program under Vitis to initialize the TDC and read timestamps from TDC, parse them and output the result over UART. A static library from Serutek will help us to realize these functionalities.
1. Export hardware and bitstream to Vitis workspace
2. Launch Vitis
Launch Vitis from the workspace, where the hardware has been exported to.
3. Create a new application
Create a new application and you'll be prompted to create a platform. Select the tab "ceate a new platform from hardware" and navigate to the xsa file that we exported in the previous steps. Complete all the steps, and a hello world application will be created.
4. Copy library and source code into the application
Create a folder under application, naming it "lib" and copy source code and header file into the folder src.
Some more settings are required to tell the linker where to find the static library. Right click on the new application and select "properties" and complete the settings as following:
5. Remember we use external SRAM to store code and data? The linker script should be modified to let the compiler be aware of it. Select the application, in the top menu navigate to "Xilinx" then click "Generate Linder Script".
By default, all the code, data and stack/heap are placed in the local memory. Change them to SRAM, represented by "axi_emc_0_MEM_xxxx". We also want to increase the stack and heap size, so that C standard library function like printf() can be used.
Finish all the settings and build the project. Now we can start testing!
A clock generation evalution board Si5341 EVB is used to generate the test pulses. SMA to Dopont 2.54mm cables are used to route pulse signal to Cmod A7. The ClockBuild Pro software from Silicon Labs are used to change the frequency and phase relationship of the test signal.
First, let's test the high speed signal. Set the Si5341 to output two in-phase clock signals of 59.1234MHz. These signals are routed to hit0 and hit1 port respectively (channel 1 and channel 2 of the TDC).
The timestamp is printed on a serial terminal (complete version in attachment), 256 samples will be recorded for each channel:
A python script is used to calculate some performance indexes and the result is presented here:
1. According to our experience, in a more advanced develop board with better clock and larger PCB, the rms(standard deviation) will be decreased by about 10ps.
2. In the ideal case, the time interval between two in-phase clocks should be 0. Here, the measured value is 1418.88 ps. This value is considered as the static offset between channels and is caused by different route length from IO to delay chain. The variation of the offset under the same temperature is under 30ps.
Histogram of channel2 - channel1
Now the input hit signals are change to two in-phase clocks of 1.2345KHz
At such a low speed hit signal, the TDC can take as much measurement(samples) as the buffer(ram) size allows. In this test, we take 4096 samples from the both channels and calculate the performance indexes(complete version of measurement data can be found in attachment):
When the frequency of the hit signal decreases, the measured time interval of each channel increases. The clock characteristics of the TDC time base will play a larger role in the measurement. For a single channel, the standard deviation of the linear residual increases dramatically, which is more obvious in the following plot:
Essentially, the curve above depicts the frequency drift between the differenct clock source of the TDC time base and the test hit signal. The source of the 4-channel TDC time base is the on board 12MHz clock. And the source of the hit signal is a 48MHz clock located on the Si5341 evaulation board. In serious TDC application, a TCXO or OCXO will be used as the TDC clock source.
However, we test in-phase clock signals in this test. Although the clock frequency is low, but the phase or time difference between the two signals is also small. For this reason, the measured time interval between channel 1 and channel 2 is hardly influenced by the clock source. Here, we get a rms resolution of about 25ps, which is quite good considering the small dimension of the Cmod A7. The histogram of the measured time difference is presented as follows:
1. Cmod A7 35T reference manual
2. TDC IP from SeruTek
www.serutek.cn (currently only in Chinese)