sdoira
Published © GPL3+

A Stereo Vision System Powered by Zynq SoC with Complete RTL

A stereo vision system with the lowest grade Zynq powered by parallel computing of FPGA. RTL and other design files are presented.

ExpertShowcase (no instructions)Over 1 day276

Things used in this project

Hardware components

ZedBoard
ZedBoard
used as a hardware prototype
×1

Software apps and online services

Vivado Design Suite
Xilinx Vivado Design Suite
Xilinx Software Development Kit
Xilinx Software Development Kit
Visual Studio 2015
Microsoft Visual Studio 2015
OpenCV
OpenCV
Autodesk EAGLE

Story

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Custom parts and enclosures

EAGLE CAD data

PCB CAD data for EAGLE 9.5.2

Schematics

Register Map

Register map of custom RTL block in excel format

schematics_WcCEtgm0GZ.zip

Schematics, board layout in PDF format and BOM file

Code

RTL.zip

Verilog
RTL and simulation source code written in Verilog-HDL for Vivado 2017.3
No preview (download only).

FW.zip

C/C++
C source code for Xilinx SDK 2017.3
No preview (download only).

App.zip

C/C++
Sample application software C++ code for Microsoft Visual Express 2015
No preview (download only).

Credits

sdoira

sdoira

0 projects • 0 followers
Developing embedded systems for over 15 years. Expertises are FPGA and PCB design.

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