This project demonstrates how to take a custom RTL module and add an AXI4-Lite interface wrapper to it for use in the Vivado block design.
As a fun start to 2022, I pulled out the HP vintage bubble displays I bought on eBay with a simple Verilog controller module on the Arty Z7.
Leveraging HLS functions to create a image processing solution which implements edge detection (Sobel) in programmable logic.
Creating an image processing platform that enables HDMI input to output. This can be used as a base for HLS-based image processing demo.
Not all imaging systems need to be expensive. Solutions can be created using cost optimized FPGA and CMOS image sensors directly.
Xilinx Pynq framework allows us to combine Python and programmable logic. Let's look at how we can create a Pynq Image for custom boards.
A tutorial on creating an UART interface between the Basys 3 board and the computer terminal in VHDL running on FPGA.
I do a lot of work with image processing and need to test cameras / imagers. I am going to create a scalable test platform.
The goal of this blog is to create a Vitis 2021.1 hardware accelerator platform for the Zybo-Z7-20 board from Digilent.
Building on the Zybo Z7 image processing application. This project demonstrates using HLS with C/C++ to accelerate image processing.
This getting started guide teaches you how to program Python on Digilent Arty Z7-20, the Xilinx Zynq Z7020 SoC platform.
Let's teach Neural Network how to do a job for us.
Interface a CMOS camera with a ZYNQ-7000 series FPGA SoC and output live video feed to a VGA screen.
This project walks through the build of an embedded Linux image for the Kria KV260 Vision AI starter kit using PetaLinux 2021.2
The ability to process, manipulate and otherwise work with audio signals is a key feature of DSP in FPGA. Here's a look at how we do this!
Find the location of a device, using multiple DWM1000-ESP8266 pairs, and an FPGA.
See how to generate a custom embedded Linux image for the Arty Z7 using PetaLinux 2020.2.
This tutorial walks through an application that reads/writes data to DDR memory from the Linux userspace on the Zynq-based Arty Z7 FPGA.
Generate a sound described by Fourier Analysis coefficients. FPGA gives a possibility of generating complex sounds in real time.
The Cortex-M1 is ideal for implementations in low-cost FPGA Spartan 7 devices. Let's look at an example project.
Bring up a base hardware design in Vivado and Vitis on the Eclypse Z7 with PMOD and ZMOD support.
This project walks through how to implement a simple FIR filter with pre-generated coefficients in Verilog.
Part one of a project that will demonstrate the building of an FPGA/SoC-based hexapod robot.
Radio that works with analog signal is implemented digitally on FPGA via VHDL.