This getting started guide teaches you how to program Python on Digilent Arty Z7-20, the Xilinx Zynq Z7020 SoC platform.

Let's learn everything about SRAM memories writing a controller in Verilog.

Let's write an efficient SRAM controller in Verilog.

In this project a 32ord FIR filter is computed by C application from PetaLinux. Input and output filter signals are synthesized by ZMOD DAC.

Most image sensors' datasheets are not public. Join me in attempting to use a RPi (v2.1)camera with FPGA without looking at its datasheet.

This project proposes the creation of a graphics library in order to generate and manipulate the graphic information only using VHDL.

Zynq US+ is an heterogeneous device with different kind of devices inside. On this project I will show you how to use all of them together.

Control an FPGA from the Linux OS. Dynamically reconfigure the FPGA from Linux user-space. Control custom hardware on the FPGA from Linux.

This reference tutorial shows the details and steps for "interfacing Avnet-FMC-HDMI converter with ZedBoard and implementing Sobel HLS IP".

This project will go trough the process of acquiring an input signal through the Zmod ADC and re-creating the signal through the Zmod DAC.

In this project I will show you how to create a custom AXI IP on Vitis, and the driver to manage it from Bare-Metal and Petalinux.

This project demonstrates how to interface with an AXI GPIO peripheral located in RTL vs in the block design in Vivado v2021.2

PYNQ is an open-source project that makes it easy to design embedded systems using Python for FPGA.

In this project we are going to implement an IIR filter in an FPGA from scratch using bilinear transform and the prewarping technique.

This project aims to create transmission line between two links using FPGA cards and solve the synchronization problems with ADPLL.

Transferring data to/from the Zynq's FPGA is an essential ingredient for integrating custom accelerators.

This guide will provide a step by step tutorial of how to add an FPGA board to Multisim and how to create and upload a PLD design to it.

In this project, we will be exploring the open-source, FPGA-friendly VexRiscV CPU Core and test it using Coremark on the Nexys A7.

Minized - Vitis Accelerated platform with PMOD SD-CARD adapter

In this project we are going to connect and configure a PCIe WWAN modem to a Zynq MPSOC using Petalinux and the Genesys ZU 5EV board.

Using the Zybo Z7, I demonstrate how to access GPIO in Genode and how to load a custom bitstream at boot time.

Using the Zybo Z7, I demonstrate how to access MMIO devices in Genode and howto switch bitstreams at run time.

Using Eclypse Z7 to generate an FSK signal and Genesys ZU for implement a single tone detector algorithm executed in the RTU.

This project walks through how to create an embedded Linux image for the Arty-Z7 using PetaLinux 2022.1