This getting started guide teaches you how to program Python on Digilent Arty Z7-20, the Xilinx Zynq Z7020 SoC platform.

Let's learn everything about SRAM memories writing a controller in Verilog.

Let's write an efficient SRAM controller in Verilog.

In this project a 32ord FIR filter is computed by C application from PetaLinux. Input and output filter signals are synthesized by ZMOD DAC.

Control an FPGA from the Linux OS. Dynamically reconfigure the FPGA from Linux user-space. Control custom hardware on the FPGA from Linux.

This project proposes the creation of a graphics library in order to generate and manipulate the graphic information only using VHDL.

Zynq US+ is an heterogeneous device with different kind of devices inside. On this project I will show you how to use all of them together.

This project will go trough the process of acquiring an input signal through the Zmod ADC and re-creating the signal through the Zmod DAC.

This project aims to create transmission line between two links using FPGA cards and solve the synchronization problems with ADPLL.

Minized - Vitis Accelerated platform with PMOD SD-CARD adapter

In this project I will show you how to create a custom AXI IP on Vitis, and the driver to manage it from Bare-Metal and Petalinux.

This reference tutorial shows the details and steps for "interfacing Avnet-FMC-HDMI converter with ZedBoard and implementing Sobel HLS IP".

This mini-project shows how to display a floating-point number on 7-segments using C/C++ HLS.

Using Eclypse Z7 to generate an FSK signal and Genesys ZU for implement a single tone detector algorithm executed in the RTU.

Step by step how to build working PYNQ on Minized with USB camera and WI-FI.

A how-to create PYNQ for Minized using EMMC memory

In this project I'll show you how to implement a BCD decoder on the BASYS 3 using the switches and the 7 segments display on the board.