Using Eclypse Z7 to generate an FSK signal and Genesys ZU for implement a single tone detector algorithm executed in the RTU.
In this project a 32ord FIR filter is computed by C application from PetaLinux. Input and output filter signals are synthesized by ZMOD DAC.
This project aims to create transmission line between two links using FPGA cards and solve the synchronization problems with ADPLL.
Let's write an efficient SRAM controller in Verilog.
This getting started guide teaches you how to program Python on Digilent Arty Z7-20, the Xilinx Zynq Z7020 SoC platform.
This project proposes the creation of a graphics library in order to generate and manipulate the graphic information only using VHDL.
Control an FPGA from the Linux OS. Dynamically reconfigure the FPGA from Linux user-space. Control custom hardware on the FPGA from Linux.
Allows quick evaluation of Power Supply Plant parameters for TI Buck_VMC_F2837xS project.
Let's learn everything about SRAM memories writing a controller in Verilog.