This getting started guide teaches you how to program Python on Digilent Arty Z7-20, the Xilinx Zynq Z7020 SoC platform.
Let's learn everything about SRAM memories writing a controller in Verilog.
Control an FPGA from the Linux OS. Dynamically reconfigure the FPGA from Linux user-space. Control custom hardware on the FPGA from Linux.
This project proposes the creation of a graphics library in order to generate and manipulate the graphic information only using VHDL.
Let's write an efficient SRAM controller in Verilog.
In this project I will show you how to create a custom AXI IP on Vitis, and the driver to manage it from Bare-Metal and Petalinux.
Zynq US+ is an heterogeneous device with different kind of devices inside. On this project I will show you how to use all of them together.
In this project a 32ord FIR filter is computed by C application from PetaLinux. Input and output filter signals are synthesized by ZMOD DAC.
This project will go trough the process of acquiring an input signal through the Zmod ADC and re-creating the signal through the Zmod DAC.
This reference tutorial shows the details and steps for "interfacing Avnet-FMC-HDMI converter with ZedBoard and implementing Sobel HLS IP".
This project aims to create transmission line between two links using FPGA cards and solve the synchronization problems with ADPLL.
Most image sensors' datasheets are not public. Join me in attempting to use a RPi (v2.1)camera with FPGA without looking at its datasheet.
In this project I'll show you how to implement a BCD decoder on the BASYS 3 using the switches and the 7 segments display on the board.
Using Eclypse Z7 to generate an FSK signal and Genesys ZU for implement a single tone detector algorithm executed in the RTU.
A how-to create PYNQ for Minized using EMMC memory
Minized - Vitis Accelerated platform with PMOD SD-CARD adapter
This mini-project shows how to display a floating-point number on 7-segments using C/C++ HLS.
This project demonstrates how to interface with an AXI GPIO peripheral located in RTL vs in the block design in Vivado v2021.2
Step by step how to build working PYNQ on Minized with USB camera and WI-FI.
In this project, we will be exploring the open-source, FPGA-friendly VexRiscV CPU Core and test it using Coremark on the Nexys A7.
This project walks through basic RF testing for hardware/software verification of SDRs on the Ettus B205mini USRP.
This guide will provide a step by step tutorial of how to add an FPGA board to Multisim and how to create and upload a PLD design to it.
Using XDMA PCIE with DDR MEMORY in Vivado