Creating custom applications is pretty straightforward in PetaLinux, but to debug them, Vitis comes into play.
See how to generate a custom embedded Linux image for the Arty Z7 using PetaLinux 2020.2.
See how to build a base hardware image for the Arty Z7 FPGA development board in Vivado 2020.2
See how to integrate your custom FIR with Xilinx DSP IP such as their DDS Compiler IP.
Continuing with my simple FIR filter Verilog module, this project walks through how to rewrite HDL logic when setup timing violations occur.
This project walks through how to implement a simple FIR filter with pre-generated coefficients in Verilog.
This project has implemented UART receiver, transmitter, and flexible Polar Encoder.
With this project, we want to create a new platform for communication.
The ability to see across multiple elements of the EM spectrum, e.g. visible IR, provides significant benefits. Let's look how we can do it.
Control an FPGA from the Linux OS. Dynamically reconfigure the FPGA from Linux user-space. Control custom hardware on the FPGA from Linux.
Sweep 'n' Play is a FPGA-based games consoles that offers you a new you way to play from your smartphone or tablet.
This getting started guide teaches you how to program Python on Digilent Arty Z7-20, the Xilinx Zynq Z7020 SoC platform.