See how to generate a custom embedded Linux image for the Arty Z7 using PetaLinux 2020.2.
This project walks through how to implement a simple FIR filter with pre-generated coefficients in Verilog.
Continuing with my simple FIR filter Verilog module, this project walks through how to rewrite HDL logic when setup timing violations occur.
Using the ADP3450, this project measures amount of delay between asserting FPGA IO on base of NPN 2N3094 and LED illuminating on collector.
The ability to see across multiple elements of the EM spectrum, e.g. visible IR, provides significant benefits. Let's look how we can do it.
See how to integrate your custom FIR with Xilinx DSP IP such as their DDS Compiler IP.
Creating custom applications is pretty straightforward in PetaLinux, but to debug them, Vitis comes into play.
See how to build a base hardware image for the Arty Z7 FPGA development board in Vivado 2020.2
With this project, we want to create a new platform for communication.
This project demonstrates how to take a custom RTL module and add an AXI4-Lite interface wrapper to it for use in the Vivado block design.
As a fun start to 2022, I pulled out the HP vintage bubble displays I bought on eBay with a simple Verilog controller module on the Arty Z7.
This project has implemented UART receiver, transmitter, and flexible Polar Encoder.