This project walks through how to implement a simple FIR filter with pre-generated coefficients in Verilog.
The ability to see across multiple elements of the EM spectrum, e.g. visible IR, provides significant benefits. Let's look how we can do it.
How to integrate DesignStart Arm Cortex-M1 and M3 processors with the Xilinx Zynq.
Creating custom applications is pretty straightforward in PetaLinux, but to debug them, Vitis comes into play.
See how to generate a custom embedded Linux image for the Arty Z7 using PetaLinux 2020.2.
See how to integrate your custom FIR with Xilinx DSP IP such as their DDS Compiler IP.
See how to build a base hardware image for the Arty Z7 FPGA development board in Vivado 2020.2
Continuing with my simple FIR filter Verilog module, this project walks through how to rewrite HDL logic when setup timing violations occur.
The SWEEP'n'PLAY console offers a new way of playing thanks to its smartphone.
With this project, we want to create a new platform for communication.
This project has implemented UART receiver, transmitter, and flexible Polar Encoder.