The ability to see across multiple elements of the EM spectrum, e.g. visible IR, provides significant benefits. Let's look how we can do it.
This project walks through how to implement a simple FIR filter with pre-generated coefficients in Verilog.
How to integrate DesignStart Arm Cortex-M1 and M3 processors with the Xilinx Zynq.
Continuing with my simple FIR filter Verilog module, this project walks through how to rewrite HDL logic when setup timing violations occur.
With this project, we want to create a new platform for communication.
See how to integrate your custom FIR with Xilinx DSP IP such as their DDS Compiler IP.
The SWEEP'n'PLAY console offers a new way of playing thanks to its smartphone.
This project has implemented UART receiver, transmitter, and flexible Polar Encoder.