FPGA-based real-time fractal generation. Fully pipelined, dynamic resource allocation, up to 18000 MMUL/s. Float matrix math on J1B CPU.
Monitoring digital circuits can be difficult at best. Sometimes it's nigh impossible. But the Digital Discovery makes it easier!
PLC with an HMI operator panel. System is able to be used with real automation objects. Showcased on miniaturized, fully-functional models.
Logic Analyzer is a project which can help students and engineers to verify digital hardware, digital communication or software integration.