PLC with an HMI operator panel. System is able to be used with real automation objects. Showcased on miniaturized, fully-functional models.
FPGA-based real-time fractal generation. Fully pipelined, dynamic resource allocation, up to 18000 MMUL/s. Float matrix math on J1B CPU.
Let's write an efficient SRAM controller in Verilog.
Here we demonstrate how to build fundamental CanSat electronics using a Cmod A7 FPGA board.
Let's learn everything about SRAM memories writing a controller in Verilog.