The goal of this blog is to create a Vitis 2021.1 hardware accelerator platform for the Zybo-Z7-20 board from Digilent.
This project aims to implement the Support Vector Machine (SVM) on a Zynq 7000 or Zynq-MPSoC board.
Moving data from traffic generator peripheral to DDR memory of Zybo Z7-10 using register mode DMA transactions
See how to create a simple traffic generator peripheral with a slave AXI4-Lite interface and a master AXI-4 streaming interface
Develop a system that can run applications that are usually run on powerful machines, on much slower and cheaper ones.
This is reference tutorial on implementing different features of Video Mixer, mainly alpha blending and logo layer and multiple TPG layers.
Fractals are great patterns to recreate in FPGA. Let's look at what they are and how to implement them.
Leveraging HLS functions to create a image processing solution which implements edge detection (Sobel) in programmable logic.
Building on the Zybo Z7 image processing application. This project demonstrates using HLS with C/C++ to accelerate image processing.
Creating an image processing platform that enables HDMI input to output. This can be used as a base for HLS-based image processing demo.