A tutorial on creating an UART interface between the Basys 3 board and the computer terminal in VHDL running on FPGA.
This simple project uses Xilinx Vitis 2020.1 to run an up/down BCD counter on Basys-3 board.
SPI Interface code for Pmod ALS (8-bit ADC) in Verilog is implemented from scratch,and transmitted to 7-seg display on Basys3 FPGA board.
This project implements a UART transmit logic design in HLS.
In this project I'll show you how to implement a BCD decoder on the BASYS 3 using the switches and the 7 segments display on the board.
This project implements a digital dice roller on Basys3 board using HLS.
This mini-project shows how to display a floating-point number on 7-segments using C/C++ HLS.
Logic analyzers can be costly, Enxor seeks to provide an open-source design to turn a FPGA into a tool for reading in/external signals.
How to control a light sensor in HLS using Basys 3 board.
This project demonstrates the capability of high-level synthesis in describing digital systems by implementing a 0-9 Up/Down counter.
The goal of this mini-project is to drive a 4-phase bipolar stepper motor using high-level synthesis for FPGA.
Using an example, this project demonstrates the impact of the combinational circuit design in HLS.
AXI-Lite registers bank. Can be monitored/changed via TCL commands. Also monitored through a seven-segment display + onboard switches.