Let's learn everything about SRAM memories writing a controller in Verilog.
In this project a 32ord FIR filter is computed by C application from PetaLinux. Input and output filter signals are synthesized by ZMOD DAC.
Let's write an efficient SRAM controller in Verilog.
Most image sensors' datasheets are not public. Join me in attempting to use a RPi (v2.1)camera with FPGA without looking at its datasheet.
Zynq US+ is an heterogeneous device with different kind of devices inside. On this project I will show you how to use all of them together.
This reference tutorial shows the details and steps for "interfacing Avnet-FMC-HDMI converter with ZedBoard and implementing Sobel HLS IP".
This guide will provide a step by step tutorial of how to add an FPGA board to Multisim and how to create and upload a PLD design to it.
In this project we are going to implement an IIR filter in an FPGA from scratch using bilinear transform and the prewarping technique.
In this project, we will be exploring the open-source, FPGA-friendly VexRiscV CPU Core and test it using Coremark on the Nexys A7.
In this project we are going to connect and configure a PCIe WWAN modem to a Zynq MPSOC using Petalinux and the Genesys ZU 5EV board.
Minized - Vitis Accelerated platform with PMOD SD-CARD adapter
Using the Zybo Z7, I demonstrate how to access MMIO devices in Genode and howto switch bitstreams at run time.
Using Eclypse Z7 to generate an FSK signal and Genesys ZU for implement a single tone detector algorithm executed in the RTU.
A how-to create PYNQ for Minized using EMMC memory
Step by step how to build working PYNQ on Minized with USB camera and WI-FI.
Using XDMA PCIE with DDR MEMORY in Vivado