See how to integrate your custom FIR with Xilinx DSP IP such as their DDS Compiler IP.
How to integrate DesignStart Arm Cortex-M1 and M3 processors with the Xilinx Zynq.
See how to generate a custom embedded Linux image for the Arty Z7 using PetaLinux 2020.2.
Creating custom applications is pretty straightforward in PetaLinux, but to debug them, Vitis comes into play.
Continuing with my simple FIR filter Verilog module, this project walks through how to rewrite HDL logic when setup timing violations occur.
With this project, we want to create a new platform for communication.
This project demonstrates how to take a custom RTL module and add an AXI4-Lite interface wrapper to it for use in the Vivado block design.
Sweep 'n' Play is a FPGA-based games consoles that offers you a new you way to play from your smartphone or tablet.
As a fun start to 2022, I pulled out the HP vintage bubble displays I bought on eBay with a simple Verilog controller module on the Arty Z7.
This project has implemented UART receiver, transmitter, and flexible Polar Encoder.