FPGA-based real-time fractal generation. Fully pipelined, dynamic resource allocation, up to 18000 MMUL/s. Float matrix math on J1B CPU.
Let's write an efficient SRAM controller in Verilog.
Monitoring digital circuits can be difficult at best. Sometimes it's nigh impossible. But the Digital Discovery makes it easier!
This project consists of making a logical analyzer, which can help us analyze digital hardware and software analysis.
Here we demonstrate how to build fundamental CanSat electronics using a Cmod A7 FPGA board.
Let's learn everything about SRAM memories writing a controller in Verilog.