AXI-Lite registers bank. Can be monitored/changed via TCL commands. Also monitored through a seven-segment display + onboard switches.
Text to speech device that can help people with low vision to read
Creating A simple Project Using Cmod S7 FPGA WIth Vivado
Using the ADP3450, this project measures amount of delay between asserting FPGA IO on base of NPN 2N3094 and LED illuminating on collector.
This project walks through the build of an embedded Linux image for the Kria KV260 Vision AI starter kit using PetaLinux 2021.2
A guide for getting a TE0802 Zynq UltraScale+ MPSoC development board up and running with Vivado/Vitis 2019.2.
See how to build a base hardware image for the Arty Z7 FPGA development board in Vivado 2020.2
This simple project uses Xilinx Vitis 2020.1 to run an up/down BCD counter on Basys-3 board.
See how to create a simple traffic generator peripheral with a slave AXI4-Lite interface and a master AXI-4 streaming interface
See how to get up and running with the new ADP3450 USB Oscilloscope to fulfill your bench top test equipment needs.
This project walks through how to implement a simple FIR filter with pre-generated coefficients in Verilog.
A tutorial on creating an UART interface between the Basys 3 board and the computer terminal in VHDL running on FPGA.
The goal of this project is to demonstrate the capability of HLS in designing a digital clock system.
PLC with an HMI operator panel. System is able to be used with real automation objects. Showcased on miniaturized, fully-functional models.
This project demonstrates the capability of high-level synthesis in describing digital systems by implementing a 0-9 Up/Down counter.
See how to bring up Xilinx's soft-processor implementation, the MicroBlaze, on the Arty-A7 board.
FPGA based binary clock, which uses GPS for the time reference.
How to control motors using PWM, the MiniZed and a touchscreen controller.
The Cortex-M1 is ideal for implementations in low-cost FPGA Spartan 7 devices. Let's look at an example project.
The ability to process, manipulate and otherwise work with audio signals is a key feature of DSP in FPGA. Here's a look at how we do this!
Python-powered edge analytics and machine learning for electric drives.