This simple project uses Xilinx Vitis 2020.1 to run an up/down BCD counter on Basys-3 board.
See how to create a simple traffic generator peripheral with a slave AXI4-Lite interface and a master AXI-4 streaming interface
See how to get up and running with the new ADP3450 USB Oscilloscope to fulfill your bench top test equipment needs.
This project walks through how to implement a simple FIR filter with pre-generated coefficients in Verilog.
This project will go trough the process of acquiring an input signal through the Zmod ADC and re-creating the signal through the Zmod DAC.
A tutorial on creating an UART interface between the Basys 3 board and the computer terminal in VHDL running on FPGA.
This project implements a UART transmit logic design in HLS.
The goal of this project is to demonstrate the capability of HLS in designing a digital clock system.
PLC with an HMI operator panel. System is able to be used with real automation objects. Showcased on miniaturized, fully-functional models.
This mini-project shows how to display a floating-point number on 7-segments using C/C++ HLS.
This project demonstrates the capability of high-level synthesis in describing digital systems by implementing a 0-9 Up/Down counter.
In this project I'll show you how to implement a BCD decoder on the BASYS 3 using the switches and the 7 segments display on the board.
In this project I will show you how to create a custom AXI IP on Vitis, and the driver to manage it from Bare-Metal and Petalinux.
See how to bring up Xilinx's soft-processor implementation, the MicroBlaze, on the Arty-A7 board.
Builds on the project Mini But Mightyu, the MiniZed and Vitis for Motor Control using the built in accelerometer to control the speed.
FPGA based binary clock, which uses GPS for the time reference.
How to control motors using PWM, the MiniZed and a touchscreen controller.
The Cortex-M1 is ideal for implementations in low-cost FPGA Spartan 7 devices. Let's look at an example project.
The ability to process, manipulate and otherwise work with audio signals is a key feature of DSP in FPGA. Here's a look at how we do this!
Connect your FPGA project to a wireless network and get information about your system while on the network.
Python-powered edge analytics and machine learning for electric drives.
This project proposes the creation of a graphics library in order to generate and manipulate the graphic information only using VHDL.