This project walks through how to implement a simple FIR filter with pre-generated coefficients in Verilog.
A tutorial on creating an UART interface between the Basys 3 board and the computer terminal in VHDL running on FPGA.
See how to bring up Xilinx's soft-processor implementation, the MicroBlaze, on the Arty-A7 board.
The Cortex-M1 is ideal for implementations in low-cost FPGA Spartan 7 devices. Let's look at an example project.
The ability to process, manipulate and otherwise work with audio signals is a key feature of DSP in FPGA. Here's a look at how we do this!
In this project I will show you how to create a custom AXI IP on Vitis, and the driver to manage it from Bare-Metal and Petalinux.
This project walks through the build of an embedded Linux image for the Kria KV260 Vision AI starter kit using PetaLinux 2021.2
This project proposes the creation of a graphics library in order to generate and manipulate the graphic information only using VHDL.
How to control motors using PWM, the MiniZed and a touchscreen controller.
See how to build a base hardware image for the Arty Z7 FPGA development board in Vivado 2020.2
Connect your FPGA project to a wireless network and get information about your system while on the network.
FPGA based binary clock, which uses GPS for the time reference.
See how to create a simple traffic generator peripheral with a slave AXI4-Lite interface and a master AXI-4 streaming interface
This project will go trough the process of acquiring an input signal through the Zmod ADC and re-creating the signal through the Zmod DAC.
In this project I'll show you how to implement a BCD decoder on the BASYS 3 using the switches and the 7 segments display on the board.
This project implements a UART transmit logic design in HLS.
This simple project uses Xilinx Vitis 2020.1 to run an up/down BCD counter on Basys-3 board.
See how to get up and running with the new ADP3450 USB Oscilloscope to fulfill your bench top test equipment needs.
A guide for getting a TE0802 Zynq UltraScale+ MPSoC development board up and running with Vivado/Vitis 2019.2.
Using the ADP3450, this project measures amount of delay between asserting FPGA IO on base of NPN 2N3094 and LED illuminating on collector.
The goal of this project is to demonstrate the capability of HLS in designing a digital clock system.
This mini-project shows how to display a floating-point number on 7-segments using C/C++ HLS.
Python-powered edge analytics and machine learning for electric drives.
This project walks through basic RF testing for hardware/software verification of SDRs on the Ettus B205mini USRP.