AXI-Lite registers bank. Can be monitored/changed via TCL commands. Also monitored through a seven-segment display + onboard switches.
This simple project uses Xilinx Vitis 2020.1 to run an up/down BCD counter on Basys-3 board.
A tutorial on creating an UART interface between the Basys 3 board and the computer terminal in VHDL running on FPGA.
This project demonstrates the capability of high-level synthesis in describing digital systems by implementing a 0-9 Up/Down counter.