Basys 3
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The Basys 3 is an entry-level FPGA development board designed exclusively for Vivado Design Suite, featuring Xilinx Artix-7 FPGA architecture. Basys 3 is the newest addition to the popular line of Basys development boards, and is perfectly suited for students or beginners just getting started with FPGA technology. The Basys 3 includes the standard features found on all Basys boards: complete ready-to-use hardware, a large collection of on-board I/O devices, all required FPGA support circuits, a free version of development tools, and at a student-level price point.

More I/O:

Double the user interface switches, double the number of onboard outputs, upgraded the number of external ports (moving from 6-pin single-row Pmods to 12-pin double-row Pmods) and included for the first time on a Basys class device a USB-UART bridge. 

Modern Architecture and Modern Programming Challenges

Due to the migration from the Spartan-3E family to the Artix-7 class of device, the Basys 3 offers a substantial increase in hardware capabilities. With the new Artix FPGA comes 15X the logic cells (from 2,160 to 33,280) and the upgrade from multipliers to true DSP slices. It also adds over 26X the amount of RAM. 

Industry's First SoC Strenth Design Suite

The most significant change to the Basys 3 is the upgrade to Xilinx Vivado Design Suite, the most modern design tool chain used by professional engineers worldwide. Compared to ISE, Vivado offers an improved user experience and expanded capabilities. These capabilities include block-based IP integration (which can reduce development time up to 10x) and the Vivado Logic/Serial I/O analyzer*.  

* Only available with Vivado Design Edition - Additional Documentation can be found on the Digilent resource center for Basys 3.

Connector(s):

  • USB A
  • USB micro-B
  • Four 12-pin Pmod ports
  • VGA

Features:

  • Features the Xilinx Artix-7 FPGA: XC7A35T-1CPG236C
  • 33,280 logic cells in 5200 slices (each slice contains four 6-input LUTs and 8 flip-flops) 
  • 1,800 Kbits of fast block RAM 
  • Five clock management tiles, each with a phase-locked loop (PLL)
  • 90 DSP slices
  • Internal clock speeds exceeding 450 MHz
  • On-chip analog-to-digital converter (XADC)
  • Digilent USB-JTAG port for FPGA programming and communication
  • Designed Exclusively for Vivado Design Suite. Expanded features are available through purchase of the Design Edition. 
  • Free WebPACK™ download for standard use.
  • USB A
  • Micro-B USB 
  • Serial Flash 
  • USB-UART Bridge 
  • 12-bit VGA output 
  • USB HID Host for mice, keyboards and memory sticks 
  • 16 user switches 
  • 16 user LEDs
  • 5 user pushbuttons 
  • 4-digit 7-segment display
  • 4 Pmod ports: 3 Standard 12-pin Pmod ports, 1 dual purpose XADC signal / standard Pmod port

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