Pablo Trujillo
Published © CC BY

Designing a Custom AXI IP on Vitis

In this project I will show you how to create a custom AXI IP on Vitis, and the driver to manage it from Bare-Metal and Petalinux.

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Designing a Custom AXI IP on Vitis

Things used in this project

Hardware components

Genesys ZU-3EG: Zynq Ultrascale+ MPSoC Development Board
Digilent Genesys ZU-3EG: Zynq Ultrascale+ MPSoC Development Board
×1

Software apps and online services

Vivado Design Suite
AMD-Xilinx Vivado Design Suite
Xilinx Software Development Kit
AMD-Xilinx Xilinx Software Development Kit

Story

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Code

Project repository

Project 00_custom_ip_acc

Credits

Pablo Trujillo

Pablo Trujillo

11 projects • 59 followers
FPGA designer for power electronics equipment. DSP and Power Electronics Control design specialist.

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