Mohammad Hosseinabady
Published © MIT

UART Transmit with HLS for FPGA

This project implements a UART transmit logic design in HLS.

BeginnerShowcase (no instructions)1 hour268
UART Transmit with HLS for FPGA

Things used in this project

Hardware components

Basys 3
Digilent Basys 3
×1
USB-A to Micro-USB Cable
USB-A to Micro-USB Cable
×1

Software apps and online services

Vivado Design Suite HLx Editions
Xilinx Vivado Design Suite HLx Editions

Story

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Code

Code snippet #1

Plain text
bool delay(long long int n) {
  static bool dummy = 0;
  for (long long int j = 0; j < n; j++) {
#pragma HLS pipeline
    dummy = !dummy;
  }
  return dummy;
}

void uart_baudrate_clock(bool &baudrate_clk) {
	static bool s = 0;
	s=!s;
	baudrate_clk = s;
	delay(5208);
}

Code snippet #2

Plain text
void uart_data_transfer(bool &uart_tx, ap_uint<8> data, bool baud_rate_clock, bool start) {
  static bool send_bit = 1;
  static bool start_state = 0;
  static bool transfer = 0;
  static unsigned int count = 0;
  static int state = 0;
  ap_uint<10> d= ((bool)0b1, (ap_int<8>)data, (bool)0b0);
  if (start == 1 && start_state == 0) {
    transfer = 1;
    start_state = 1;
    count = 0;
  }

  if (start == 0 && start_state == 1) {
    start_state = 0;
  }
  if (baud_rate_clock == 1 && state == 0 && transfer == 1) {
    send_bit = d[count++];
    if (count == 10) {
      transfer = 0;
    }
    state = 1;
  }

  if (baud_rate_clock == 0 && state == 1) {
    state = 0;
  }
  uart_tx = send_bit;
}

Credits

Mohammad Hosseinabady

Mohammad Hosseinabady

6 projects • 2 followers
Mohammad Hosseinabady has a PhD degree in Computer and Electronics Engineering. He is an expert in High-Level Synthesis for FPGAs.

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