Mohammad Hosseinabady
Published © MIT

Stepper Motor Controller in High-Level Synthesis

The goal of this mini-project is to drive a 4-phase bipolar stepper motor using high-level synthesis for FPGA.

IntermediateFull instructions provided1 hour31
Stepper Motor Controller in High-Level Synthesis

Things used in this project

Hardware components

Basys 3
Digilent Basys 3
×1
Pmod STEP
Digilent Pmod STEP
×1
Usongshine Nema 17 Stepper Motor 42BYGH
×1

Software apps and online services

Vivado Design Suite HLx Editions
Xilinx Vivado Design Suite HLx Editions

Story

Read more

Code

Code snippet #1

Plain text
typedef enum {s0, s1, s2, s3} stepper_motor_state;
void bipolar_stepper_motor( bool motor_clk_rate, ap_uint<4> &motor_signal) {
#pragma HLS INTERFACE ap_none port=motor_signal
#pragma HLS INTERFACE ap_none port=motor_clk_rate
#pragma HLS INTERFACE ap_ctrl_none port=return
	static stepper_motor_state state=s0;
	stepper_motor_state next_state=state;
	ap_uint<4> motor_signal_tmp;
	switch (state) {
			case s0:
				if (motor_clk_rate == 1) {
					next_state = s1;
				} else {
					next_state = s0;
				}
				motor_signal_tmp = 0b1000;
				break;
			case s1:
				if (motor_clk_rate == 1) {
					next_state = s2;
				} else {
					next_state = s1;
				}
				motor_signal_tmp = 0b0010;
				break;
			case s2:
				if (motor_clk_rate == 1) {
					next_state = s3;
				} else {
					next_state = s2;
				}
				motor_signal_tmp = 0b0100;
				break;
			case s3:
				if (motor_clk_rate == 1) {
					next_state = s0;
				} else {
					next_state = s3;
				}
				motor_signal_tmp = 0b0001;
				break;
			default:
				break;
		}
	state = next_state;
	motor_signal = motor_signal_tmp;
}

Code snippet #2

Plain text
int main() {
	int status = 0;
	bool       motor_clk_rate;
	ap_uint<4> motor_signal;
	motor_clk_rate = 0;
	for (int i = 0; i < 20; i++) {
		for (int j = 0; j < 5; j++) {
			bipolar_stepper_motor ( motor_clk_rate, motor_signal);
			motor_clk_rate = 0;
			std::cout << "motor_signal = " << std::setfill ('0') << std::setw (4) << (std::bitset<4>)motor_signal << std::endl;
		}
		motor_clk_rate = 1;
	}
	return status;
}

Code snippet #3

Plain text
##Sch name = JC7
set_property PACKAGE_PIN L17 [get_ports {motor_signal[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {motor_signal[0]}]
#Sch name = JC8
set_property PACKAGE_PIN M19 [get_ports {motor_signal[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {motor_signal[1]}]
#Sch name = JC9
set_property PACKAGE_PIN P17 [get_ports {motor_signal[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {motor_signal[2]}]
#Sch name = JC10
set_property PACKAGE_PIN R18 [get_ports {motor_signal[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {motor_signal[3]}]

Credits

Mohammad Hosseinabady

Mohammad Hosseinabady

9 projects • 20 followers
Mohammad Hosseinabady has a PhD degree in Computer and Electronics Engineering. He is an expert in High-Level Synthesis for FPGAs.

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