Mohammad Hosseinabady
Published © MIT

Digital Dice Roller in HLS

This project implements a digital dice roller on Basys3 board using HLS.

IntermediateFull instructions provided1 hour16

Things used in this project

Hardware components

Basys 3
Digilent Basys 3
×1
USB-A to Micro-USB Cable
USB-A to Micro-USB Cable
×1

Software apps and online services

Vivado Design Suite HLx Editions
Xilinx Vivado Design Suite HLx Editions

Story

Read more

Code

Code snippet #1

Plain text
ap_uint<32> pseudo_random(ap_uint<32> seed, bool load) {
#pragma HLS INLINE off
  static ap_uint<32> lfsr;

  if (load ==1 )
    lfsr = seed;
  bool b_32 = lfsr.get_bit(32-32);
  bool b_22 = lfsr.get_bit(32-22);
  bool b_2 = lfsr.get_bit(32-2);
  bool b_1 = lfsr.get_bit(32-1);
  bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
  lfsr = lfsr >> 1;
  lfsr.set_bit(31, new_bit);

  return lfsr;

}

Code snippet #2

Plain text
void dice_roller(
		ap_uint<8>  &seven_segment_data,
		ap_uint<4>  &seven_segment_enable,
		bool         first_player,
		bool         second_player

		) {
#pragma HLS INTERFACE ap_ctrl_hs port=return
#pragma HLS INTERFACE ap_none port=second_player
#pragma HLS INTERFACE ap_none port=first_player
#pragma HLS INTERFACE ap_none port=seven_segment_enable
#pragma HLS INTERFACE ap_none port=seven_segment_data

	static int state   = 0;
	static ap_uint<8>  segment_data = svn_sg_code[0];
	static ap_uint<4>  segment_enable = 0b1111;

	if (state == 0) {
		pseudo_random(11, 1);
		state = 1;
	} else {
		pseudo_random(0, 0);
	}

	if (first_player == 1) {
		ap_uint<32> r = pseudo_random(0, 0);
		ap_uint<4> dice      = r%6 + 1;
		segment_data   = svn_sg_code[dice];
		segment_enable = 0b1110;

	} else if (second_player == 1) {
		ap_uint<32> r = pseudo_random(0, 0);
		ap_uint<4> dice      = r%6 + 1;
		segment_data   = svn_sg_code[dice];
		segment_enable = 0b0111;
	} else {
		ap_uint<32> r = pseudo_random(0, 0);
	}

	seven_segment_data   = segment_data;
	seven_segment_enable = segment_enable;
}

Credits

Mohammad Hosseinabady

Mohammad Hosseinabady

4 projects • 1 follower
Mohammad Hosseinabady has a PhD degree in Computer and Electronics Engineering. He is an expert in High-Level Synthesis for FPGAs.

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