For working with this project, you just need to have ZedBoard or one of FPGA Board [ZC706/ZC702/PZ7030_FMC2/ PZ7020_FMC2/ MZ7020_FMCCC], Avnet FMC HDMI Converter module, one or two USB cables, power adapter for the Board, HDMI Input and HDMI Output Cable, Display monitor [1080p].Reference Project
We reference Zedboard.org project, i.e “FMC-HDMI-CAM + PYTHON-1300-C Frame Buffer Design Tutorial” or “FMCHC_PYTHON1300C_Tutorial_2016_4_01.pdf”provided at http://zedboard.org/support/design/1521/11.Sobel Edge Detection HLS IP
We have created the Sobel IP in HLS as of the Xilinx Application Note [XAPP1167] Sources [or you can use other sobel HLS implementation to], we just created this IP for 1080x1920p resolution as of our requirement. We have synthesized, Run the C Simulation and verified the Sobel Implementation on HLS tool and then exported the HLS design as IP to the VIVADO Tool.
The Sobel IP can process the real time AXI Stream Frames of RGB Pixels [24 bit] into the Sobel output of RGB 24 Bit.
While the default design we just have created used YCbCr type of Pixel representation so we will need to have convert that pixel value in to RGB of 24 bits. For this conversion we will use the “chroma resampler” and then YCrCb into RGB converter and vice versa after getting output from the Sobel IP.ZedBoard FMC HDMI Sobel IP design explained
This IP design use the YCbCr 422 based IP’s such as the “Video On Screen Display, so the output processed pixel frame must be of YCbCr 422 format. The IP configuration of “Video On Screen Display”:
Video Pipeline [main section]
The explanation of the above zoomed section is presented below:1. Chroma Resampler
This IP converts the Image Frames/Pixels from YCbCr 422 into YCbCr 444 format.
This IP converts the YCrCb 422 format of pixel values into the RGB format. So that out Sobel IP can process the pixel values and generate the output of RGB.
Sobel has not had any option to customized. It is static IP. It process the RGB 24 bit pixels Stream and generate the RGB 24 bit edge detected image frames.
That frame needs to send to the Video On Screen Display and the AXI4-Stream to Video out IP for display port connection.
For this purpose, we are going to use the YCbCr IP and the chroma resampler again to generate the YCbCr 444 output pixel data to the “Video on Screen Dsiplay”.4. RGB to YCrCb
Now this IP converts the sobel output RGB pixel into the YCrCB 444 format.
Chroma resampler IP here converts the YCrCb 444 pixel into the YCrCb 422 format which is necessary to send to the “Video On Screen Display”.
Since we are introducing the “Sobel Edge Streaming” IP on the default design, so there is no need to update other things on the design. Cause Streaming IP just takes the AXI stream and gives the AXI Stream, so there is no control lines or “S_AXI_CTRL” lines.
Here is the FMC-HDMI converter connection setup with ZedBoard. We are taking HDMI-in from FMC-HDMI converter and sending HDMI-out to FMC-HDMI converter.
For the complete demonstration, we can also use Python1300C camera with FMC-HDMI converter.
Default ZedBoard FMC HDMI project [without sobel] of VIVADO 2018.3 can be downloaded from: Link
For Complete VIVADO project of ZedBoard HDMI+ Sobel, please write us at: email@example.com. For using VIVADO project, the board setup and VIVADO version need to be checked on so we need email!